The analog supplies are usually powered before the I/O supply, but this is not the case for all ADCs. To avoid forward biasing the ESD diodes and powering up the digital core in an unknown state, turn on the I/O supply before the interface circuitry. Application Note AN-932, Power Supply Sequencing, provides a good reference for designing supplies for these ADCs. Decoupling capacitors with short traces should be connected between the V IO pin and DGND.ĪDCs that operate with multiple supplies may have well-defined power-up sequences. The digital inputs should generally be between DGND − 0.3 V and V IO+ 0.3 V to avoid violating the absolute maximum ratings. This pin should be at the same voltage as the host interface (MCU, DSP, or FPGA) supply. Most SAR ADCs provide a separate digital I/O power-supply input, V IO or V DRIVE, which determines the operating voltage and logic compatibility of the interface. Digital I/O Power-Supply Level and Sequence This article discusses design techniques for reliable, integrated digital interfaces, including the digital power-supply level and sequence, I/O state during turn on, interface timing, signal quality, and errors caused by digital activity. Their advantages include small size, low power, no pipeline delay, and ease of use.Ī host processor can access or control the ADC via a variety of serial and parallel interfaces such as SPI, I 2C, and LVDS. Successive-approximation analog-to-digital converters, called SAR ADCs due to their successive-approximation register, are popular for applications requiring up to 18-bit resolution at up to 5 MSPS. Design Reliable Digital Interfaces for Successive-Approximation ADCs
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